1. Field of the Invention
The present invention generally relates to a buffer amplifier, and more particularly, to a half-power buffer amplifier adaptable to a liquid crystal display (LCD).
2. Description of Related Art
A liquid crystal display (LCD) typically includes rows and columns of picture elements (or pixels) arranged in matrix form. Each pixel includes a thin film transistor (TFT) and a pixel electrode formed on a substrate (or panel). The gates of the TFTs in the same row are connected together through a gate line, and controlled by a gate driver (or scan driver). The sources of the TFTs in the same column are connected together through a source line, and controlled by a source driver (or data driver). A common electrode is formed on another substrate (or panel). A liquid crystal (LC) layer is sealed between the pixel electrode substrate and the common electrode substrate, and for each pixel the voltage difference between the pixel electrode and the common electrode determines the display of the pixel(s).
As the resolution of the LCD increases, thousands of output buffer amplifiers or buffer circuits should be built into the source driver. As a result, the LCD, particularly the large-size and/or high-resolution LCD, consumes immense power. On the other hand, as the power is precious to any portable electronic device with such an LCD, the power consumption of the LCD therefore tends to determine the available run time of the entire portable electronic device. Accordingly, an LCD with low-power buffer amplifiers is becoming indispensable, and some schemes, such as half-power buffer amplifiers have been proposed.
FIGS. 1A-1B show conventional half-power buffer amplifiers 10 and 12. Regarding the display of a first frame, referring to FIG. 1A, the amplifier 10 for the first channel CH1 generates the first half power (e.g., VDD to VDD/2) as the output OUT1 through a switch S1 (as indicated by the solid arrow). At the same time, the amplifier 12 for the second channel CH2 generates the second half power (e.g., VDD/2 to ground) as the output OUT2 through a switch S4 (as indicated by the solid arrow).
Subsequently, regarding the display of a second frame, the amplifier 12 for the second channel CH2 generates the second half power (e.g., VDD/2 to ground) as the output OUT1 through a switch S3 (as indicated by the dashed arrow). At the same time, the amplifier 10 for the first channel CH1 generates the first half power (e.g., VDD to VDD/2) as the output OUT2 through a switch S2 (as indicated by the dashed arrow).
As shown in FIG. 2, during the display of the first frame, the output OUT1 is used to drive the first row of the LCD, and the output OUT2 is used to drive the second row of the LCD. Subsequently, during the display of the second frame, the output OUT2 is used to drive the first row of the LCD, and the output OUT1 is used to drive the second row of the LCD. In other words, the same pixel (such as the circled pixel shown in FIG. 2) with respect to different frame(s) is driven by different amplifier(s) 10/12. As a result, the offsets incurred from different amplifiers cannot be properly cancelled, thereby degrading the display quality.
For the reason that the conventional half-power amplifiers cannot effectively cancel their offset voltages while decreasing power consumption, a need has thus arisen to propose a novel scheme or circuit in order to resolve the offset cancellation issue.